Design high-speed PCB channels in your browser: pick the laminate, budget the loss, size the traces and check against PCIe and Ethernet standards. Results update as you type.
Join the WaitlistRequest DemoBrowser-based tools for high-speed PCB channels: choose the material, budget the loss, size the traces and check the result against the interface standard.
Step-by-step channel setup: laminate selection, Tx-to-Rx loss budget, trace impedance, net groups, stackup and bump map. Closed-form models (Hammerstad–Jensen, IPC-2141) update as you type.
Join the waitlist →Vias, microstrip, grounded CPW, stripline, wire bonds and SMA, 2.92, 2.4 and 1.85 mm connectors. Sweep geometry and filter datasets by impedance, insertion loss and return loss.
Browse the library →Compare every channel with PCIe Gen3–Gen6, 10G and 25G-KR and 100G PAM4 budgets: insertion loss, differential impedance, laminate loss and return-path checks in one table.
Join the waitlist →Set data rate and loss budget; compare laminates by loss, thermal limits and cost.
Lay out each link from Tx to Rx (packages, routes, vias, connectors) against its loss budget.
Solve trace width for a target impedance, with S-parameters and eye diagram.
Group nets into buses and clocks with length-match and via limits.
Build the stackup and assign each group to a signal layer next to a reference plane.
Lay out the bump map and assign nets, ground and power.
Check every channel against PCIe and Ethernet budgets and impedance limits.
Impedance, loss, delay and S-parameters come from closed-form models that run in your browser, so every change updates at once. Measured data sits on the same plots for comparison.
The laminate you pick sets trace impedance and stackup, channel routes name the trace types, and the standards check reads every channel, trace and layer. Change one input and the rest follow.
Wherever a channel has to meet a loss budget or an impedance limit.
PCIe Gen3–Gen6 and 10G to 100G Ethernet channels, from laminate choice to loss budget.
Bump maps, wire bonds and package-to-board transitions.
Grounded CPW, stripline and precision connectors up to 67 GHz.
Overlay measured S-parameters on the model to see where they disagree.
The formulas behind the models, their sources and valid ranges, and six considerations.
Read the article →How many solver runs a sensitivity study needs, and how to predict where the response curves.
Read Part A →Why simulated and measured responses disagree, and five ways engineers close the gap.
Read the article →Join the waitlist and we'll email you when your access is ready.
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